GPIF-II Master example project not working | Cypress Semiconductor
GPIF-II Master example project not working
Summary: 4 Replies, Latest post by A.K. on 23 Feb 2015 08:29 AM PST
Verified Answers: 0
19 Feb 2015 08:43 AM PST#1
I am looking at the example project of GPIF-II Master downloaded from http://www.cypress.com/?rID=84236 .
I tried simulating the timing diagram on GPIF-II designer and it gives me error for WRITE operation (data from master to slave) in transition of WR_DATA_WAIT to COUNT_HIT saying invalid state machine path, see the attached picture.
I didn’t change anything and just made a timing scenario on GPIF designer with sequence of
START → RD_WR_IDLE → WR_FLAG → WR_DATA → WR_DATA_WAIT → COUNT_HIT → RD_WR_IDLE.
It didn’t give errors when I simulate it until WR_DATA_WAIT, as soon as I added COUNT_HIT it shows the error.
However, the project was built successfully (without changing anything). Is the state machine still gonna work despite the error? Is the WRITE operation gonna work?
How can the error be solved?
Could someone from Cypress explain why this is?
If anyone have any idea, would be greatly appreciated..
Thank you very much!