GPIF II Designer questions | Cypress Semiconductor
GPIF II Designer questions
I have a question with regard to the GPIF II Designer:
I am trying to create a simple local bus interface where the FX3 is the master and have noticed that whenever I describe a group of states to perform a read of a slave that the IN_DATA action appears to want the data bus to be driven by the slave at least 1 state early if not 2 depending on how you want to look at it. The attached jpg file is a screen shot of the timing diagram created by GPIF II Designer and in the state machine IN_DATA is an action in the FIFO_RD_1ST state. I wouldn't expect the data to have to be valid until at least that state if not the one after depending on how IN_DATA is treated.
I don't have a software resource available yet or I would just try it to find out the answer. At this point I am just trying to charcterize the interface to see what is possible and how best to utilize the FX3 in our designs.