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GPIF II Design. Load FPGA Image + Sync FIFO | Cypress Semiconductor

GPIF II Design. Load FPGA Image + Sync FIFO

Summary: 2 Replies, Latest post by RickL on 18 Oct 2013 02:34 PM PDT
Verified Answers: 0
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RickL's picture
25 posts


my goal is to develop a firmware for the FX3 that would do the following:

- 1. Load the FPGA Image from the computer to the Altera Cyclone FPGA we are using

- 2. Set up the FX3 in Sync FIFO with the FPGA as slave

for the second task, the firmware example provided syncfifo2bits is very close to my application, and I plan to help myself from it.

However, I have the Cypress FX3 DVK but not the Altera DVK, so unfortunately no way to load the Altera image without finish the first task previously.

It seems to be a rather common application, is there any example available I could start with ? or documents ? I feel like I read almost the whole FX3 library but have not found much explanation on this process.

thanks for any feedback

rskv's picture
Cypress Employee
1134 posts

 Hi Rick,

The following application notes shows you how we can load bit file into an FPGA.

AN84868 - Configuring an FPGA over USB Using Cypress EZ-USB® FX3™

But this one is tested with Xilinx Spartan - 6 FPGA. FPGA is configured over Slave serial interface. I looked at the Slave Serial interface of Altera FPGA and I did not find any difference. So this should directly work with Altera FPGA as well. You need to connect to the right hardware pins after you get the Alter DVK.

The example project attached to this application note configures the FPGA and then FX3 re-configures itself to function as Slave FIFO interface. Please refer to the above mentioned application note for more details. Let me know if you have any questions related to this topic.


Sai Krishna,



RickL's picture
25 posts

 thanks for your answer.

I looked into more details of my FPGA configuration, and it is actually a rather odd pin wiring.

The only solution that I can think about is configuring the lines as simple GPIOS and Toggling the DCLK & DATA[0] manually. There is no way to toggle several GPIOs simulatenously, so this will result the data rate to be 1/4th of the GPIO rate.

I have 2 choices to implement this solution:

- Writing a cpp code that will send the fpga image bit by bit through USB Vendor commands

- Writing a cpp code that will send the fpga image to EP0, writing a firmware that would read EP0, and do the bit by bit transfer to the FPGA of the EP0 data.

which solution would be the best for my project ?




(Here are the connected pins if needed:)
GPIO25 > DATA[0]
pulled high > nSTATUS (no bridge connection)
INIT_DONE not connected to the bridge either.


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