GPIF II Design. Load FPGA Image + Sync FIFO | Cypress Semiconductor
GPIF II Design. Load FPGA Image + Sync FIFO
my goal is to develop a firmware for the FX3 that would do the following:
- 1. Load the FPGA Image from the computer to the Altera Cyclone FPGA we are using
- 2. Set up the FX3 in Sync FIFO with the FPGA as slave
for the second task, the firmware example provided syncfifo2bits is very close to my application, and I plan to help myself from it.
However, I have the Cypress FX3 DVK but not the Altera DVK, so unfortunately no way to load the Altera image without finish the first task previously.
It seems to be a rather common application, is there any example available I could start with ? or documents ? I feel like I read almost the whole FX3 library but have not found much explanation on this process.
thanks for any feedback