GPIF DMA Flags and IN endpoints | Cypress Semiconductor
GPIF DMA Flags and IN endpoints
I have the GPIF controller configured in 32bit synchronous master mode hooked up to an FPGA. I have exported several DMA flags one of them being Thread_0_DMA_Ready, which I use with an IN endpoint. The output DMA flag going to the FPGA is mostly at 0 even if I send multiple IN packets to the FX3. Experimenting with the setup, I found that even when the DMA flag is 0, I can successfully capture and transfer data to the PC (via IN_DATA). My state machine knows to stop capturing data based on the internal GPIF DMA_RDY_TH0 conditional flag, and does not use LD_DATA_COUNT or CMP_DATA_COUNT. As soon as GPIF state machine sees that the internal DMA_RDY_TH0 is 0, it switches to an idle state and this is the only time I see the output DMA flag Thread_0_DMA_Ready going to 1. The output DMA flag stays high for roughly 80 cycles (at 100MHz) then goes down low. Is this behavior expected?
Basically, I would like to know what does Thread_0_DMA_Ready indicate when used with an IN endpoint? It seems to me as if though Thread_0_DMA_Ready does not simply mimic the value of the internal conditional falg DMA_RDY_TH0.
Should I look I be thinking of Thread_0_DMA_Ready from the FX3 USB's perspective? As in, the IN endpoint thread is "ready" when it has data available to send to the USB controller?