GPIF control out hold time? | Cypress Semiconductor
GPIF control out hold time?
The data sheet specifies a tCTLO (clock to out valid) time of 8ns and a tCOH (clock to out hold) of 0ns. If this is true then there aren't many devcies that will interface with the CYUSB3014 including another CYUSB3014 or a high speed synchronus FIFO which both require 0.5ns of hold time on a control input. In my case the CYUSB3014 will be the GPIF master and driving the clock and controls.
I'm looking for clarification of this timing spec.