GPIF cannot work at 100MHz clock | Cypress Semiconductor
GPIF cannot work at 100MHz clock
I encounter an problem when about using GPIF at 100MHz in synchronous-slave-fifo-write mode.
The scenario is as below:
the pclk is 100MHz, SLWR write 16KB to GPIF, and switch the FIFO ADDR. But after SLWR sending the next 16KB, the flagb will be valid, and keep valid all the time. Then SLWR could not write data any more, so did GPIF.