Getting started with a slave fifo design, and a question about data retention | Cypress Semiconductor
Getting started with a slave fifo design, and a question about data retention
I am sketching out a data acquisition design where I want to have a 24-32 bit data source asynchronously feed data into the FX3, to then be passed on to software running on the host PC.
Before I start doing board layout I want to be sure that I set up the GPIF II interface properly.
Could someone point me towards the GPIF II design software and suggest which options I should start with for streaming high speed data from ADCs running from a separate clock source into the GPIF II interface (expecting 50-70 MHz on the 32 bit bus).
My second question is about data retention. I want to be able to upload some settings to the unit that will be non volatile. Is it safe to write to the start or end of the eeprom chip that is used as boot memory, or should I put a 2nd eeprom chip on to hold nvm user settings.
Thanks in advance.