FX3: Why does 32-bit Slave Fifo conflict with SPI? | Cypress Semiconductor
FX3: Why does 32-bit Slave Fifo conflict with SPI?
The CYUSB301x manual (001-52136 Rev. *N), states: "When GPIF II is configured for the 32-bit data bus width, GPIO-GPIO may be configured as GPIOs or I2S, and GPIO to GPIO may be configured as
GPIOs or UART interface only."
Could someone elaborate on exactly why the SPI peripheral becomes unavailable when using a 32-bit GPIF II bus? I see no physical pin conflicts; GPIO - GPIO  certainly don't overlap the GPIF II data or control signals, as far as I can tell.
I assume there must be some internal signal muxing/routing conflict, or other internal resource contention? If so, could someone share some details on this?