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FX3 Sync Slave FIFO: 2 additional words on read | Cypress Semiconductor

FX3 Sync Slave FIFO: 2 additional words on read

Summary: 2 Replies, Latest post by Rover on 23 May 2013 04:31 AM PDT
Verified Answers: 0
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Chris R.'s picture
143 posts

No I have the FX3 DVK board connected to our FPGA board and try to set up the sync slave FIFO connetion. If I send data from host to the OUT EP, the FX3 delivers 2 additional words before the transmitted data. How can I setup the FX3 correctly to avoid this? I set up the endpoints and sockets in this way:


#define CY_FX_EP_PRODUCER               0x06    /* EP 6 OUT */
#define CY_FX_EP_CONSUMER               0x82    /* EP 2 IN */

#define CY_FX_EP_PRODUCER_USB_SOCKET    0x06    /* USB Socket 6 is producer */
#define CY_FX_EP_CONSUMER_USB_SOCKET    0x02    /* USB Socket 2 is consumer */

/* Used on FX3 silicon. */
#define CY_FX_EP_PRODUCER_PPORT_SOCKET    CY_U3P_PIB_SOCKET_0    /* P-port Socket 0 is producer */
#define CY_FX_EP_CONSUMER_PPORT_SOCKET    CY_U3P_PIB_SOCKET_1    /* P-port Socket 1 is consumer */

And set up the GPIF II to connect the flags fixed to the threads:


    {CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(4)      , 0x00000011},    //FLAGA = Fixed to Thread 1
    {CY_U3P_PIB_GPIF_CTRL_BUS_SELECT_ADDRESS(5)      , 0x00000010},    //FLAGB = Fixed to Thread 0


This works well, but there are 2 cycles with 0x0000 data in the FIFO. Do I have to use the partial flags with watermark value? Is yes, how to configure?

Attached you can find the ChipScope output for this beha

Chris R.'s picture
143 posts

Argh, some errors:

the last word schould be "behavior"

I sent only the words 0x1111, 0x2222, 0x3333, 0x4444 and 0x8000 to the OUT EP.

Rover's picture
48 posts

There is 2 clock cycles' delay once fx3 enters "output" mode.

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