FX3 superspeed kit - SPARTAN 6 SP601 - FIFO | Cypress Semiconductor
FX3 superspeed kit - SPARTAN 6 SP601 - FIFO
I am using the superspeed FX3 kit together with the SP601 from xilinx. i have conneted them as shown in AN65974 and I am using the provide STREAM_IN firmware and the VHDL code.
I am trying to set up this data flow:
FPGA (number generator) -> sync FIFO (in the FPGA) ->FX3 superspeed (STREAM_IN) -> PC (streamer application)
So I modified part of the provided VHDL code introducing my number generator and my FIFO memory.
I would like the FX3 to read my FIFO by controlling the read_enable only when these conditions are met:
(PROG_EMPTY or EMPTY )= '0'
I know that when both FLAG_A and FLAG_B from the FX3 are HIGH the state machine (implemented in VHDL) goes in write mode and DATA can be written in the FX3 buffer. SLWR goes low then FLAG_B goes low too --> write_delay mode.
Can somebody help?
Thank you in advance