FX3 slave fifo Stream Out data error problems | Cypress Semiconductor
FX3 slave fifo Stream Out data error problems
I use DE2-115 FPGA board to transfer data via CYUSB3014 mini board. The stream in data transfer is relatively easy as the document said and I haven't found any problem. But the stream Out transfer I tried so many times and still not finished yet.
The problem I met is, for example, when I transfer 512Bytes data, FPGA can actually receive 520Bytes. I observed the transport waveform and found several clock data bus will be zero.
So I wonder how did you finished slave fifo transfer successfully and did you use the Verilog code provided by Cypress?
Thank you very much.