FX3 Slave FIFO Partial Packet | Cypress Semiconductor
FX3 Slave FIFO Partial Packet
I've read through AN65974 regarding the Synchronous Slave FIFO mode, and the associated FPGA example design. It seems like the examples cover the GPIF cases where there is a full DMA buffer transfer, then a partial or zero-length transfer. What about the case where the host is sending a partial packet to the FX3, like 128 bytes? Is it possible to notify the FPGA there is data to be read from the FX3? It seems like FlagC does not go high until the DMA buffer is completely full? Is that correct?