FX3 Slave FIFO FLAG | Cypress Semiconductor
FX3 Slave FIFO FLAG
I config FX3 as Slave FIFO 32bit.
If I set FLAGA is Thread_0_DMA_Ready, FLAGB is Thread_0_DMA_Watermark, and set watermark as 4.
Assume DMA buffer is 1024*4.
Because the write is random, I assume the flowing steps:
1. Write 1019 words to fifo;
2. Because no data, wait some cycles;
3. Write 2 words to fifo; (I think FLAGB is not active, because 3 cycles latency)
4. Because no data, wait some cycles, now FLAGB is active;
5. Now data arrived, but we cannot know how many space at DMA buffer? FLAGB=L, FLAGA=H, ( actual has 3 words space);
I think, at step 5, we can only use single write cycle? For example, write one word, and wait 4 cycles, then check the FLAGA?