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FX3 Slave FIFO 32-bit won't work: AN65974 | Cypress Semiconductor

FX3 Slave FIFO 32-bit won't work: AN65974

Summary: 2 Replies, Latest post by leva on 07 Jul 2016 04:06 AM PDT
Verified Answers: 0
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apelsinapa_1597131's picture
1 post

We've just got started testing the FX3 (CYUSB3014-BZXI) on a custom board, connected to a FPGA as in the AN65974: Designing with the EZ-USB® FX3™ Slave FIFO Interface.
With the SlaveFifoSync example configured at 16 bits and a 100 Mhz PCLK, the cypress streamer application recieves data at 179000KB/s. Then when the firmware is changed with the CY_FX_SLFIFO_GPIF_16_32BIT_CONF_SELECT = 1 nothing works.

The FPGA is a configured with the state machine from the provided vhdl code.

FLAGA/FLAGB is inactive, so the fpga remains in idle mode - transfer never starts. All FX3 init code checks out without any errors, new GPIF design for 32-bit with GPIF2 designer don't seem to work either.

We're obviously missing something...?

(Meanwhile we'll continue search the forums for similar problems - no exact match found yet)

mady's picture
Cypress Employee
964 posts


With the change in the bus width from 16 to 32, the watermark value passed to the CyU3PGpifSocketConfigure API should also be changed in your firmware.

To calculate the watermark value to be passed, please refer the formulae in AN65974 Application Note.


- Madhu Sudhan

leva's picture
24 posts


And after changing watermark you should properly setup dma buffer.


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