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FX3 Programming FPGA example code - can't see any debug info over UART | Cypress Semiconductor

FX3 Programming FPGA example code - can't see any debug info over UART

Summary: 2 Replies, Latest post by Igi_sh on 20 Jun 2016 03:45 AM PDT
Verified Answers: 0
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Igi_sh's picture
2 posts

Hi Guys,


Need your help regarding an UART issue I'm having in my custom board design.

I've burned the onboard I2C EEPROM with SlaveFifo example (from AN65974), with several

CyU3PDebugPrint() of my own. In this case I see my debug info printed on UART on a terminal.

However, when I'm burning the FPGA programming example (from AN84868), with

 several debug messages of my own, I see no any UART debug info on terminal, even

after I have successfully programmed the onboard FPGA.

I probably missing something obvious here, but up to this point, can't really understand

what might be the reason to absence of debug messages?

Please let me know if you need more details to understand the root cause.


Thank you in advance.

mady's picture
Cypress Employee
955 posts


The AN84868 project uses SPI Interface as well in addition to UART. From Table 7 of FX3 Datasheet, when both SPI and UART are used, the UART pins are mapped to GPIOs 46 to 49. But when UART interface alone is used as in An65974 project, the UART pins are mapped to the GPIOs 53 to 56.

In your custom board you would have connected the UART pins to 53 to 56. So you did not get the debug prints.

However, in the AN84868 project, after you have switched to Slavefifo mode (after finishing configuring the FPGA), the SPI is disabled, and now you can get the UART Debug Prints from 53 to 56.


- Madhu Sudhan

Igi_sh's picture
2 posts


Thank you for your answer.

Well, to my surprise I'm not getting any output on UART after switching.

I'm not that greedy, I need the UART to debug the slaveFifo application (after the switch).

I was playing around with the code and actually narrowed it down to SPI configuration.

As long as SPI is not being configured I'm getting the output as I should, but obviously,

in this case I can't configure FPGA.

Any additional thoughts why the IO matrix reconfiguration is not working as it should?



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