FX3 Layout Support - Microstrip Impedance | Cypress Semiconductor
FX3 Layout Support - Microstrip Impedance
I'm starting a new layout of a design using the FX3 device. I've carefully read the Hardware Guidelines for the FX3 and still cannot understand a couple things:
1) There is a recommendation of a ~11mil trace width and a 8mil space for the superspeed microstrip lines. From the development kit's fab drawing, I see that there is a bit of a bizarre stackup which yields a 90 Ohm differential impedance (edge-coupled) on these lines with a 12mil trace and 8 mil space. This is all fine, but unfortunately it causes some fairly large 19mil 50-ohm single ended traces! I have a fairly tight design, so I need reasonable ~5-8mil 50 Ohm traces on the top and bottom layers for routing. Is there a reason why the stackup was chosen to give these large traces? Is there a loss factor that I am not considering? I have a stackup that will give the 90 Ohms edge-coupled differential impedance with a ~6/8/6mil microstrip.
2) B-Type routing: I've decided to use a more rugged full size b-type connector and it is been a fairly painful experience so far. Would it be very unwise to keep the routing (as the attachment shows) on the same side as the connector? I understand that a 'stub' is created from this, but I have no idea on how to gauge the effect. Would it be better to run all of these signals through a set of vias, as recommended (with the ground vias appropriately spaced)? In my mind, it seems that introducing the layer change would be worst than the stub created, but I would definitely like to hear someone's informed opinion.
I would definitely like to hear from the experts on this one, thank you!