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FX3 to FPGA read latency | Cypress Semiconductor

FX3 to FPGA read latency

Summary: 1 Reply, Latest post by Madhu Sudhan on 23 Dec 2015 03:19 AM PST
Verified Answers: 0
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beandigital's picture
48 posts

I have a design where I want to read some data from the Fx3 PPORT to an FPGA using the slave interface. I am using a 8-bit bus. I am finding that the data takes 3 clocks from setting the SLRD signal low. I read in the datasheet that it is supposed to be 2. So I am a bit confused why I am getting 3.


mady's picture
Cypress Employee
963 posts


The extra clock cycle is when you see it from FPGA's perspective. FX3 takes only 2 clock cycles to latch the data, the one more clock cycle is required by FPGA to sample it.


- Madhu Sudhan

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