FX3 EP1IN on FPGA and EP2IN/OUT on RX/TX UART parallel access issue | Cypress Semiconductor
FX3 EP1IN on FPGA and EP2IN/OUT on RX/TX UART parallel access issue
What I want to do is to have a FPGA configuration IN/OUT port over the FX3 UART and connected to USB EP2, AND a high throughput FPGA data port connected to GPIF and mapped with EP1IN.
I've configured the FX3 EP1IN with GPIF for the FPGA reading (FPGA writes to GPIF and DMA to USB) with FX3 DMA AUTO : works fine alone
I've configured the FX3 EP2IN & OUT for UART RX/TX (according to firmware sample) with USB to UART in DMA AUTO, and UART to DMA in DMA MANUAL (DMA handle is doing CyU3PDmaChannelCommitBuffer() and pktsPending++ flag with is read in a thread loop which executes CyU3PDmaChannelSetWrapUp() upon (pktsPending==0) every 40ms, like fw example) : works fine alone
On Win7 using CyUSB.net, I'm using 3 threads :
- 1 background thread (highest priority) is still running and continuously read data from EP2IN (UART) with XferData() and put data in a queue for the main app which can read the queue afterwards : works fine alone and with EP2OUT, I can send and receive bytes over the FX3 UART
- 1 command/answer thread can be launch from the main app in order to send a command over the UART (directly use XferData() on EP2OUT) and receive with some latency the answer by reading the queue filled by the 1st thread : works fine alone and with EP2IN & OUT, I can send and receive bytes over the FX3 UART
- 1 data thread (highest priority) can be launch in order to get high bandwitdh data from EP1IN in bulk mode
So now what I do is :
- launch the background thread : Lecroy analyzer shows EP2IN Transaction Packet H->D ACK and a EP2IN D->H Data Packet (len=0) every 40ms => OK, FX3 thread wrapUp the DMA channel
- launch the data thread, waiting for FPGA data on EP1IN : OK
- launch the start command (EP2OUT) and receive (EP2OUT) the acknowledge from FPGA which ask to the FPGA to push data over GPIF => EP1IN : OK : Lecroy analyzer show the cmd and answer on EP2IN/OUT and right afterwards the EP1IN transfers with data len = 1024. This continues until I want to stop it from a stop command.
- 1st remark : the EP2IN TP& DP disappear while EP1IN is running while I've set the same priority for the 2 threads, and I do Thread yield for allowing both threads to have access to the USB XferData()
- When I launch the stop command on EP2OUT, I see it on the Analyzer and the FPGA stops the data flow on EP1IN and send its answer over the UART but I never receive any answer on EP2IN. On the scope I see the FPGA answer over the FX3 RX signal correctly so I suppose it is caught by the FX3 UART and the DMA. It seems the EP2IN is stuck (see previous remark)
- is there any priority with the EP number (i.e.EP1 has priority over EP2) either in windows or the FX3 fw.
- do you have any example on windows for managing in parallel 2 EP ?
You may find the Lecroy data file attached with some markers corresponding to start/stop commands/answers and the EP1 data start