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FX3 address pins | Cypress Semiconductor

FX3 address pins

Summary: 1 Reply, Latest post by michael.brown_1558351 on 03 Feb 2016 08:38 PM PST
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michael.brown_1558351's picture
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I'm having some confusion about how the FX3 assigns the address pins based on the configuration file generated using the GPIF II Designer tool. I am using the SuperSpeed explorer kit and I would like to have a master interface with a 9-bit address bus; the designer tool shows me that the following GPIOs are assigned to the  address bus:

GPIO[46:49], GPIO[29:25]

I have the state machine trying to drive the address bus using DR_ADDR, which is reading from Register (not socket). In the firmware I have a loop that increments a variable, i, from 0 to 4 and I am writing this value to the register using CY_U3P_PIB_GPIF_EGRESS_ADDRESS(0) = &i

I have probed the GPIOs assigned by the designer, but I see no change in the output.

When I look in the FX3 technical reference manual there is a comment for the ADR_CTRL bit field in the GPIF_BUS_CONFIG register that says the following:

"Number of control lines overridden by address lines. Control signals CTRL[15] to CTRL[16-
ADR_CTRL] are not connected to pins. Instead those pins are designated as address signals. Which
address signals depends on the other mode fields above. In other words: if ADR_CTRL = 0 all CTRL
lines are connected to pins, if ADR_CTRL = 1, CTRL[15] is not connected and so on."

However the datasheet does not specify any pins that have the name CTRL[14] or CTRL[13] (see Table 7 for CYUSB1304) and this comment does not agree with the GPIOs assigned by the Designer tool. 

I am going to try and test the address bus output by driving using counter, just to make sure I am not having a board issue, but any clarification on the above would be appreciated.


michael.brown_1558351's picture
2 posts

I think I figured out what my problem is. I suspect there may be a bug in how the address pins are assigned depending on the configuration chosen in the GPIF Designer tool. My intended interface was:

  • master
  • 16 bit data bus
  • 9 bit address bus
  • 2 inputs
  • 6 outputs

First of all, there is a comment in the data sheet that with a 16-bit data bus, the GPIF allows 16 configurable control pins (not sure if that includes use of the unused 16 data bits as they technically aren't control pins), so I'm not sure if there's an issue with having 17 signals + 16 data bits. The Designer tool doesn't throw an error, so I assumed it was ok. 

I found that in the FX3 Programmers Manual there is a table (3-1) that shows which GPIOs are mapped to certain peripherals depending on the configuration (GPIF+UART for example). There is also another table (3-4) that shows the GPIF I/O connections for various configurations. 

For my particular configuration, 35-pin 16b data, not multiplexed address, it shows the assigned pins for A[0:11]. However, according to table (3-1) it shows GPIF I/O [42:45] as NC, but that's where A[0:3] are supposed to be mapped??

I tried testing things will fewer address pins and noticed that at some point the Designer tools drops the higher number I/O and reassigns them to GPIO 29 and lower. In this case it works. This may be because once I dropped the total number of pins low enough, the Designer tool reconfigures the GPIF_BUS_CONFIG register to have the 31-pin GPIF configuration, not the 35-pin configuration, thus shifting where the address pins are mapped.

For the moment I am getting around this issue by overriding the address pins and driving them as GPIOs from the firmware. This is less than ideal, especially for anyone needing high speed communication. 

Can anyone confirm this, and/or suggest a possible fix??





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