FX3 address pins | Cypress Semiconductor
FX3 address pins
I'm having some confusion about how the FX3 assigns the address pins based on the configuration file generated using the GPIF II Designer tool. I am using the SuperSpeed explorer kit and I would like to have a master interface with a 9-bit address bus; the designer tool shows me that the following GPIOs are assigned to the address bus:
I have the state machine trying to drive the address bus using DR_ADDR, which is reading from Register (not socket). In the firmware I have a loop that increments a variable, i, from 0 to 4 and I am writing this value to the register using CY_U3P_PIB_GPIF_EGRESS_ADDRESS(0) = &i
I have probed the GPIOs assigned by the designer, but I see no change in the output.
When I look in the FX3 technical reference manual there is a comment for the ADR_CTRL bit field in the GPIF_BUS_CONFIG register that says the following:
"Number of control lines overridden by address lines. Control signals CTRL to CTRL[16-
ADR_CTRL] are not connected to pins. Instead those pins are designated as address signals. Which
address signals depends on the other mode fields above. In other words: if ADR_CTRL = 0 all CTRL
lines are connected to pins, if ADR_CTRL = 1, CTRL is not connected and so on."
However the datasheet does not specify any pins that have the name CTRL or CTRL (see Table 7 for CYUSB1304) and this comment does not agree with the GPIOs assigned by the Designer tool.
I am going to try and test the address bus output by driving using counter, just to make sure I am not having a board issue, but any clarification on the above would be appreciated.