FPGA CLK when designing an EZ-USB FX3 SlaveFifo Interface | Cypress Semiconductor
FPGA CLK when designing an EZ-USB FX3 SlaveFifo Interface
I'm currently working with the Superspeed Explorer Kit (CYUSB3KIT-003) to communicate with an FPGA ( type Altera Cyclone IV ). I'm following what's written on the application note AN65974 in which it is specified that the FPGA is functioning at 100 MHz with 32-bit data and that the FX3 master clock must be set to a little more than 400 Mhz.
- What does that exactly mean : why does the FX3 have to be 4 times faster than the FPGA?
- Does changing both FPGA and FX3 clocks is possible ? I'm obliged to work with only 50 MHz' FPGA : Can I communicate with my Superspeed Explorer Kit with this frequency knowing that I only want a 16-bit data bus ???
- Does changing the clocks affects the transfer rate of the USB 3.0 ?
Thanks in advance for your answers, I really really need them