FIFO requirement running on Windows | Cypress Semiconductor
FIFO requirement running on Windows
I have a FX3 application which streams data from a FPGA to an application running on the PC. I have a SDRAM that acts as a large FIFO to buffer data when Windows locks out my application from reading streamed FPGA data. I hardly ever see the SDRAM being required to buffer data and when it does it's only for 1-2ms worth of data (my PC is a mid-range spec). It seems that I could potentially do away with the SDRAM and implement multiple DMA buffers (~300K) in a 512K FX3 part instead.
I know there are so many variables here and it's very indeterminate but I'm interested in peoples' experience of the worst case duration for streamed data being held up by Windows. Any thoughts / comments welcome!