Extra I2C (bit-banging) bus on I2S pins on a CX3 | Cypress Semiconductor
Extra I2C (bit-banging) bus on I2S pins on a CX3
Hello everybody, due to different voltage levels of some I2C slave devices I need to implement a secondary I2C master on the GPIO_51 (SCL) and GPIO_52 (SDA) on a CX3 device. Usually these pins are shared with the I2S block I2S_SD and I2S_WD but it seems that they can be used as GPIO as well.
I was wondering if there is any configuration in the I/O matrix that can reassign the CX3 hardware I2C master signals to these two pins and if not (most likely not possible ) what will be the best strategy of use for a bit-banging I2C master.
I have seen from some other knowledge base articles methods of increasing the bit-bang I2C clock by calling functions that bypass the libraries checks when toggling SCL.
I didn't see any advice of switching the SDA pin form input to output and vice-versa.
Can some of the Cypress staff or forum members offer some advice or even better, direct me to some sample code if that exists.
Many tanks, MC