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EPSWITCH confusion | Cypress Semiconductor

EPSWITCH confusion

Summary: 3 Replies, Latest post by Jasper van Bourgognie on 11 Mar 2016 02:45 AM PST
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tdean's picture
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Two questions on the use of EPSWITCH to switch between physical sockets in 5-bit slave FIFO mode:

1) AN68829 timing diagrams show SLCS# low during EPSWITCH# assertion, yet KBA90268 says SLCS should be high. One of these is in error, probably KBA90268, correct? 

2) AN68829 states that when asserting EPSWITCH# to wait until FLAGA (DMA_READY) becomes 1, indicating data is available, before deasserting EPSWITCH#. But what about the (likely) case where we're switching to a Read-from-FX3 socket that doesn't have any data available in it? In that case FLAGA is low (empty) and will stay low. We can't get stuck waiting for data here while other sockets need handling. If we implement a timeout (how long?) to exit an incomplete EPSWITCH, what state (which physical socket) are we leaving that thread in? Did it successfully switch to the new physical socket even though flagA never deasserted?

mady's picture
Cypress Employee
964 posts

1)  SLCS# should be low during EPSWITCH# assertion. You can confirm this in the state machine of 5 Bit SlaveFifo Interface available in "Cypress Supplied Interface" section in GPIF II Designer tool

2) For the timing upto which EPSWICTH is asserted, please refer the following KB

We are sorry for the confusion caused by the documents. These will be updated soon.


- Madhu Sudhan

Jasper van Bourgognie's picture
2 posts

I am also confused but when I follow the link in (2) it tells me I am not authorized to access the page.

Jasper van Bourgognie's picture
2 posts

I'm currently considering to move from 2bit to 5bit slave fifo, and have exactly the same question as your 2nd one regarding the timeout.

Since you posted this a year ago, I was hoping you figured this out by now and perhaps you could explain how you figured the whole EPSWITCH to FLAG relation is?


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