EPSWITCH confusion | Cypress Semiconductor
Two questions on the use of EPSWITCH to switch between physical sockets in 5-bit slave FIFO mode:
1) AN68829 timing diagrams show SLCS# low during EPSWITCH# assertion, yet KBA90268 says SLCS should be high. One of these is in error, probably KBA90268, correct?
2) AN68829 states that when asserting EPSWITCH# to wait until FLAGA (DMA_READY) becomes 1, indicating data is available, before deasserting EPSWITCH#. But what about the (likely) case where we're switching to a Read-from-FX3 socket that doesn't have any data available in it? In that case FLAGA is low (empty) and will stay low. We can't get stuck waiting for data here while other sockets need handling. If we implement a timeout (how long?) to exit an incomplete EPSWITCH, what state (which physical socket) are we leaving that thread in? Did it successfully switch to the new physical socket even though flagA never deasserted?