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Easiest way to implement a USB<->SPI byte/packet level transfer? And architecture questions... | Cypress Semiconductor

Easiest way to implement a USB<->SPI byte/packet level transfer? And architecture questions...

Summary: 1 Reply, Latest post by RSKV on 12 Aug 2012 01:30 AM PDT
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NVergunst's picture
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I am used to dealing with microcontrollers where the USB data is put into an array that can be accessed at the byte level. So you call a doUSB() function, you get a 64byte packet of data from the host, process, and send back a 64byte packet. Or receive a byte array all the time and then send out byte arrays all the time by just checking if the endpoint is clear to do so or not.

So looking at the FX3 sample code is daunting. I can make the GPIO sample wiggle a PWM pin and so it works.

But now I just want to be able to pass the information out of the USB module into a peripheral and into another chip like an FPGA to do some light work and pass it pack through the peripheral and back into the USB module. Like a FIFO in for USB data from the host to the device and a FIFO out for USB data from the device to the host.

Since there are impossibly tiny Samtech and Tyco connectors on the dev board to access the Slave FIFO, I am forced to use the SPI header. I read that it can go 33MHz which is fine for initial testing. I am hoping I can move to the slave FIFO once I get an actual board spun with an FPGA and the FX3 on it. But for now it will be 2 dev kits wired together with some jumper wire.

So back to the firmware, I am looking at the USBSpiRegMode example (although I still dont understand the difference between RegMode and DMA mode) because it seems like a good base to go from USB to SPI. I don't know if I know what I am looking at.

I see uint8_t glEp0Buffer[4096]; which appears to be Endpoint 0's byte array buffer. Is that correct?

 It also looks like the USB mode is not a Write-then-Read architecture but an architecture that splits the write and reads from the endpoint into separate entitites so that you could write forever without reading or visa versa read forever without writing. Correct?

It would appear that CyU3PUsbGetEP0Data() is the magic USB goo that checks the USB endpoint from the host to the FX3 and when there is data it will return the data in the buffer, correct?

So this bit of code...

            status = CyU3PUsbGetEP0Data (length, glEp0Buffer, NULL);

...gets "length" bytes from EndPoint 0 (EP0) and puts them into glEp0Buffer, with returned_data's index-0 at glEp0Buffer's index-0? Is this a blocking call until data is received or does it fail the status if there is nothing to read?

Then to transfer on the Spi peripheral it uses this bit of code immediately afterwards correct?

            if (status == CY_U3P_SUCCESS)
                status = CyFxSpiTransfer (index, length,
                        glEp0Buffer, CyFalse);

It would also appear that to send data over USB, you would call CyU3PUsbSendEP0Data(length, buffer pointer) correct?

So would it stand to reason that I could simple stay in a loop that called CyU3PUsbGetEP0Data() and get a byte stream back that I could then pass into CyFxSpiTransfer()  for the Host->FPGA communication? Then pass that returned SPI byte array into CyU3PUsbSendEP0Data() for the FPGA->Host communication?

Any help would be appreciated.


rskv's picture
Cypress Employee
1134 posts





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Meanwhile, I would recommend you to create a tech support case so that one of our engineer will work on this in parallel to help you.


sai krishna.

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