does DMA_RDY_TH0 has latency? | Cypress Semiconductor
does DMA_RDY_TH0 has latency?
In AN65974,It says a three-cycle latency for the dedicated flag is always incurred at the end of the transfer,The three-cycle latency is from the write cycle that causes the buffer to become full to the time the flag is asserted low.Now i design a GPIF state machine, and use IN_DATA action,DMA_RDY_TH0 transition.
does the DMA_RDY_TH0 has latency? when I use DMA_RDY_TH0 and DMA_RDY_TH1 as state transition between IN_DATA with two threads, it seems some data lost.