DMA_RDY_TH1 and !DMA_RDY_TH1 output transitions from the same state | Cypress Semiconductor
DMA_RDY_TH1 and !DMA_RDY_TH1 output transitions from the same state
It seems GPIF II does not allow a single node to have both DMA_RDY_THx and !DMA_RDY_THx output transitions from the same state. The state machine can be built, but the timing simulation fails with error "Invalid state machine path for the simulation for state XX", where XX is the state where goes the !DMA_RDY_Thx transition. See attached example project.
Is this a bug or intended limitation of GPIF II? It would seem that if a predicate condition is allowed for a transition, so should be the negation of this predicate.
Is there a workaround for this? For instance can LOGIC_ONE be used in place of the !DMA_RDY_THx condition? What is the semantics of LOGIC_ONE for one transition used along with other condition for another transition from the same state, and what would be the state machine behavior in such case?
Thanks in advance