DMA help | Cypress Semiconductor
I am using trying to get the slave fifo design from the app note working. I am using my own verilog code in the FPGA. I have managed to get the read from the slave to work and I can transfer 512 bytes into the FPGA. With the write I have flag a as the DMA ready for thread 0. I write 512 bytes into the buffer but the flag never changes. I have also tried it as the current thread ready and the A1:0 pins set low, but still nothing. Anyone have any ideas what could be the problem.