DMA flags Basic doubt | Cypress Semiconductor
DMA flags Basic doubt
Hi i would lie to rest all the DMA Flag doubts that has been a bother for a while.
- For writing to Slave Fifo ie FPGA to GPIF
A current thread DMA RDY flag shows logic high or logic low (when the Buffer is Full/Not Full) ?
- For reading from Slave Fifo ie GPIF to FPGA
A current thread DMA RDY flag shows logic high or logic low (when the Buffer is Empty/NotEmpty)?
Now regarding partial flags..
- Can we use the partial flag to check the to- be- written GPIF socket( by FPGA) . If it is not asserted we can judge that there must be space to be written ..right?? is it essential that we need a DMA ready flag for starting a transfer..
"DMA_RDY" is actually a signal that is asserted when there is no DMA buffer available to satisfy the request."
Is this a valid conclusion .