DMA buffers full signal | Cypress Semiconductor
DMA buffers full signal
I'm testing the streaming in configuration as mentioned in AN65974, although I modified the VHDL in order to send
an increasing counter toward FX3.
The data that I get in Control Center whenever I press "Transfer data in" are not linked in the sense that the last number of the previous transfer isn't equal to the first number minus 1 of the next transfer.
I need a full memory signal from DMA in order to avoid overwriting data and another signal that notice me that data has been read from control center.
How can I do that?