Designing with the EZ-USB® FX3 Slave FIFO Interface | Cypress Semiconductor
Designing with the EZ-USB® FX3 Slave FIFO Interface
my question is related to synchronous slave FIFO interface which I want to convert to AXI4-Stream interface.
The documents used are:
The direction in question is from an external device to EZ-USB FX3 chip (writing).
1. Is possible to assert SLWR simultaneously with SLCS (with ADDR and DATA IN loaded), or is it necessary to assert SLCS at least one cycle before asserting SLWR? In the state transition diagram in the GPIF II Designer there ate two transtions (from IDLE to ADDR and from ADDR to WRITE).
2. When ADDR is set and SLCS is asserted, how long does it take to FLAG signal to be valid?
In the figure 11 in [1, page 22] it seems to be valid one cycle after SLWR asserted (or what does the dashed line from the rising edge of PCLK mean?). The table 10 in [1, page 22] notes three cycles latency from ADDR to DATA/FLAG.
3. Is possible to have more FLAGS than two actually provided by the slave FIFO interface (e. g. for every thread)? If so, what changes are necessary to make?
I would like to have the throughput as high as possible without unnecessary waiting cycles.
I am looking forward to your answers.