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CYUSB3KIT-003 EZ-USB® FX3 CONTROL PINS | Cypress Semiconductor

CYUSB3KIT-003 EZ-USB® FX3 CONTROL PINS

Summary: 2 Replies, Latest post by sm_1893366 on 02 Nov 2016 11:08 AM PDT
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sm_1893366's picture
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On the CYUSB3KIT-003 EZ-USB® FX3™ SuperSpeed Explorer Kit where do I connect the "SLCS#, SLRD#, SLWR#, SLOE#, and A[1:0] signals? The DQ[15:0] are marked but all other signals are labeled as CTL[12:0]. The GPIFII designer assigns GPIO_xx pins (Ex: GPIO_17 for SLCS#) but I cant find any information how the GPIO pins are connected to the J6 or J7 40 pin headers. 

I checked the schematic and the pins are marked as CTL[12:0] and not GPIO_xx. 

rjredman's picture
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2 posts

There is a super speed Explorer kit user guide with GPIF connector pinout listed in the hardware section.

There is a table in the device data sheet listing GPIO/CTLx  the "CYUSB303X" pdf, go to GPIOs

sm_1893366's picture
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Thanks. I found it. It is in the CYUSB303X datasheet. 

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