CYUSB3KIT-003 EZ-USB® FX3 CONTROL PINS | Cypress Semiconductor
CYUSB3KIT-003 EZ-USB® FX3 CONTROL PINS
On the CYUSB3KIT-003 EZ-USB® FX3™ SuperSpeed Explorer Kit where do I connect the "SLCS#, SLRD#, SLWR#, SLOE#, and A[1:0] signals? The DQ[15:0] are marked but all other signals are labeled as CTL[12:0]. The GPIFII designer assigns GPIO_xx pins (Ex: GPIO_17 for SLCS#) but I cant find any information how the GPIO pins are connected to the J6 or J7 40 pin headers.
I checked the schematic and the pins are marked as CTL[12:0] and not GPIO_xx.