Could someone check my Slave FIFO Stream Out state machine? | Cypress Semiconductor
Could someone check my Slave FIFO Stream Out state machine?
I finished the stream in transfer successfully but met big trouble with stream out transfer. The Verilog file provided by the vendor is hard to read so I try to write it by myself and depend on the document “AN65974 Designing with the EZ-USB® FX3™ Slave FIFO Interface”.
This is a brief stream out state machine I drew .
Idle----->Wait flag----->read----->read end -----> Idle
(I will also check the dedicated flag B)
In state Wait flag, both OE and RD is high, and may wait several clock.
In state read, I read 253 data, and BOTH OE and RD is low.
In state read end, I read 2 data, OE is low but RD is high.
I always can't transfer data correctly and could someone help me?
Thanks a lot.