Confusion with current thread flag latency | Cypress Semiconductor
Confusion with current thread flag latency
I have some confusions with the update of the current thread flags.
The chapter "Current Thread Flag" in the AN describes, that the FLAG is updated after two cycle with an valid address. But the timing diagram of the Sync. slave FIFO Write describes, that the flag is updated after 3 cycle from SLWR. Therefore I lost data. Furthermore in this timing diagram the flag is a dedicated flag and I thought, that dedicated flags can always be observed?
What is right?