confusing data lose in many_to_one DMA channel | Cypress Semiconductor
confusing data lose in many_to_one DMA channel
I get a problem of my FX3 superspeed design, and it has confused me for two weeks, so please help me.
In my design I use many_to_one DMA channel which has 2 valid socket and every socket has 4 valid buffers，my problem is everytime I start a new transfer I always lose random data after 8buffers have transfered，beside this my data received is continuous.
I am sure that FPGA always sends data a little later than PC receives data.