You are here

About slave fifo clk | Cypress Semiconductor

About slave fifo clk

Summary: 1 Reply, Latest post by RSKV on 11 Jul 2012 06:42 AM PDT
Verified Answers: 0
Last post
Log in to post new comments.
Poturaju's picture
31 posts


In Slave firo sync operation, while the SLWR is asserted, data will be written into the FIFO, on every rising edge of the CLK and the FIFO pointer is incremented. 

Here my question is that, is there any option to sample the data from data bus on the falling edge of the CLK.



rskv's picture
Cypress Employee
1134 posts

 Have you tried changing the "Active clock edge" to "Negative" in the "Interface Definition" page of the GPIF II designer project.


sai krishna.

Log in to post new comments.