About FX3 Slave FIFO Stream Out Timing Problem | Cypress Semiconductor
About FX3 Slave FIFO Stream Out Timing Problem
HI, In the document AN65974 Designing with the EZ-USB® FX3™ Slave FIFO Interface, figure3 in page5 described the Stream Out timing diagram and in page 30 there is a state machine for Stream out. I think they are not correspond to each other. I'm so puzzled and my Verilog code does not work well.
The sequence diagram says that we should assert slrd 2 clock before read data, and deassert slrd 2 clock before end. But the state machine says that rd_oe_delay and od_delay take place after read step. Could somebody tell me about the detail of the timing and how to write the state machine?
Thanks a lot and best wishes.