5-bit ADR_CTRL for 2-bit synchronous slave FIFO? | Cypress Semiconductor
5-bit ADR_CTRL for 2-bit synchronous slave FIFO?
I am having trouble getting a 32-bit synchronous slave FIFO design to accept data with SLWR#. In trying to debug this, I noticed that even though I specified 2 address bits in GPIF-II Designer, the resulting register configuration generated by the tool appears to request 5 address bits:
0x000010AC, /* CY_U3P_PIB_GPIF_BUS_CONFIG */
Based on this code in <gpif_regs.h>, I expected a config value of 0x104C:
Number of control lines overridden by address lines. Control signals
CTRL to CTRL[16-ADR_CTRL] are not connected to pins. Instead those
pins are designated as address signals. Which address signals depends
on the other mode fields above; see architecture spec for details. In
other words: if ADR_CTRL=0 all CTRL lines are connected to pins, if ADR_CTRL=1,
CTRL is not connected and so on.
#define CY_U3P_GPIF_ADR_CTRL_MASK (0x000001e0) /* <5:8> R:RW:0:No */
Even the cyfxgpif_syncsf.h in the (ostensibly 2-bit address) SDK slfifosync example appears to be configured this way.
Is this a bug in GPIF-II designer? Is it required to tie CTL[8:10] to zero for 2-bit slave FIFO designs?