32 bit FIFO loopback transfer test | Cypress Semiconductor
32 bit FIFO loopback transfer test
I've connected the FX3 DVK with a XIlinx SP605 DVK through a bridge board like the one made by Agile.
The setup is similar to the one mentioned in your AN65974 eccept for the FPGA DVK.
I'm trying to test the loopback following your application note step by step, of course i've previously adapted the pin of the FPGA.
Everything fine until step #8:
"Now the FPGA is already in a state where it is waiting for FLAGA to equal 1. As soon as the data is available in the buffer of PIB_SOCKET_0, the FPGA will read it. The FPGA will then loopback the same data and write it to FX3’s PIB_SOCKET_3."
Now when i try to loop it back with the FPGA in step #9:
"Now from the USB host you can issue a Bulk IN transfer. Select the BULK IN endpoint in Control Center and click on Transfer Data IN. The same data that was previously written is now read back."
the control center gives me error:
"BULK IN transfer
BULK IN transfer failed with Error Code:997"
What is wrong?