The QDR Consortium officially specifies input-clock phase jitter as cycle-to-cycle jitter which measures the change in clock period measurement between any two adjacent clock cycles.
Mathematically, it can be represented as:
Tcycle (n) – Tcycle (n+1)
where Tcycle (n) and Tcycle (n+1) are any two adjacent cycles measured on controlled edges.
Suppose the part is operated at 250 MHz. Then the K clock period should be ideally 4 ns.
1. For zero jitter, Tcycle (n) =Tcycle (n+1) =4 ns.
2. If Tcycle (n) =4 ns and Tcycle (n+1) = 3.9 ns, then the jitter would be (4 ns-3.9 ns) =0.1 ns. This calculated jitter should be less than or equal to the tKC Var parameter specified in the datasheet for proper operation