"Reference Schematic Design Recommendation for QDR-DDR II/II+/Xtreme SRAMs - KBA84386" www.cypress.com/ states that Vtt and Vref are both VDDQ/2, but that they have separate capacitor banks. Why the distinction?
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It is better to have two different circuits for generating VTT and Vref. In this case the voltage variations becasue of Vterm will not affect Vref.
So separate decoupling network for VTT and Vref is preffered.
Thank you PRIT!