QDRII/II+ and DDRII/II+ SRAMs must be powered up and initialized in a predefined manner to prevent undefined operations. Two voltages are applied during power up– Vdd (the core voltage) and Vddq (the I/O voltage).
Internal to the SRAM is a PLL or DLL circuit. A PLL design is used in 65nm devices and a DLL design is used in 90nm devices. The DOFF# signal enables and resets the PLL or DLL circuit internal to the SRAMs.
Please refer to the Power Up Sequence Waveforms shown in the corresponding QDRII/II+ and DDRII/II+ datasheet. The following two power up sequences can be implemented:
Power up Sequence – with DOFF# always tied High
1. Apply Vdd before Vddq or at the same time as Vddq.
2. Apply Vddq before Vref or at the same time as Vref
3. Wait for the input clock K/K# to stabilizes
4. Wait an additional 20us before starting memory operations
Power up Sequence – using the DOFF# control input
1. Start with DOFF# Low.
2. Apply Vdd before Vddq or at the same time as Vddq.
3. Apply Vddq before Vref or at the same time as Vref
4. Drive DOFF# High only when the input clock K/K# has stabilized
5. Wait an additional 20us before starting memory operations
It is highly recommended to follow the Power up Sequence which uses the DOFF# input control. The reason is because there have been issues with the internal memory DLL/PLL circuit locking to the wrong frequency when unstable clocks are applied during power up. The frequency is usually a harmonic or sub-harmonic of the operating frequency. This will result in failure during the memory read cycle because the echo clocks will be wrong.
By controlling the DOFF# input during power up, the internal memory DLL/PLL circuit will not attempt to lock until stable clocks are presented. This method of initialization prevents the DLL/PLL from locking onto the wrong frequency at power up. Thus, avoiding the problem altogether.