Why is the SER for an SRAM so much lower than that of a DRAM ?
It would seem that the larger SRAM cell would inherently have better SER?
I should have stated as SRAM has much worse SER than DRAM (e.g. SRAM SER is 250 FIT while DRAM is 50 FIT)
One reason for this is that the smaller size in DRAMs allows less charge collection; another reason is that cell size has scaled faster than storage capacitance], so the capacitance ratio has actually increased.
For more details refer to the attached whitepaper.
I realize this is an old post (over a year ago), but maybe someone is still watching?
Anyway, I'm interested in 'endurance' (yes, strange question to ask for SRAM), however, what would the 'quantitative' measurment for 'write endurance' on an Async SRAM device? How many time can I WRITE to the device before I see a failure on the READ (non matching data)? Has 'anyone' (anywhere) run this type of test? If so, who? How long? And what was the result? Thanks
From the physical point of view there is a big difference between SRam and Flash/EEProm: SRam cell consists of transistors only which form a bi-stable circuit. An EEProm or Flash contain a barrier which is tunneld (by a handful of electrons) and so keeps some charge thus changing the state. This tunneling stresses the barrier, so that it fails after some thousands to some million tunnelings. An SRam cell does not have such a barrier. As long as the sram stays within its defined specs (Temp, Voltage etc) it will live for about 20 years, then, caused by diffusion of water into the chip-housing, the tracks may corrode and then fail. This behaveour does not significantly correspont to the number of reads or writes of an SRam cell.