QDRll+ memory Termination | Cypress Semiconductor
QDRll+ memory Termination
In the qdrll+ memory controller ,
Case 1: The ODT is enabled (LOW) RQ=182ohms then input impedance = 182/3.33 is 54.65ohms and output impedance is 182/5 is 36.4 ohms, for the kit is working fine.
Case 2 : The ODT is enabled (HIGH) RQ=182 ohms then input impedance=182/1.66 is 109.6 ohms and output impedance is 182/5 is 36.4 ohms , for the kit is working fine.
How the termination are made. I am in confuse that it is giving the output for the both cases is correct. May i know how this works.