qdrll+ memory controlle rwith sram | Cypress Semiconductor
qdrll+ memory controlle rwith sram
Summary: 3 Replies, Latest post by subashbabu on 02 Aug 2013 04:47 AM PDT
Verified Answers: 1
31 Jul 2013 02:57 AM PDT#1
I want to know the number of the cycles till CQ/CQ# is stable.In the xilinx IP-Core it is given that 2048 cycles for the clock stable .
PART no :CY7C25632KV18.