QDR II+ IBIS model mismatch | Cypress Semiconductor
QDR II+ IBIS model mismatch
We are working on simulations using one of your memory component : CY7C25652KV18. We are using your IBIS model, named : qdr2pb4l25_cy25xx2.ibs in date of December 1st, 2010.
when using the INPUT models with internal ODT (for example INPUT525_TSF_1.8), it seem that the signal is centered on 500mV, but the expected value is 900mV (Vref = Vcc/2). There is also another problem on the INPUT525_TT_1.5 model which has inconsistent results for slow and fast corners.
What do you advice for the use of these models ? Do you have some updates for these models that could solve the problems mentionned above ?