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PLL Startup cycles | Cypress Semiconductor

PLL Startup cycles

Summary: 1 Reply, Latest post by PRIT on 30 Sep 2011 12:30 PM PDT
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Bits's picture
22 posts

Earlier your SRAM spec indicated that the PLL Lock time was a minimum of 1024 cycles

Now I find that the 65nm products have changed this to 20us.

what if I have an existing design that uses 1024 cycles ?

What about backward compatibility?

prit's picture
Cypress Employee
59 posts



That's a really good question!


You can still use 1024 cycles as a minimum PLL Lock time for our 65 nm products.

In this specification, Cypress surpasses the QDR consortium specification for PLL lock time (tKC lock) of 20 µs (min. spec.) and will lock after 1024 clock cycles (min. spec.), after a stable clock is presented, per the previous 90 nm version. 

But in the future higher speed designs, it won't be the same as 1024 clock cycles or 20 uS.




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