PLL Startup cycles | Cypress Semiconductor
PLL Startup cycles
Summary: 1 Reply, Latest post by PRIT on 30 Sep 2011 12:30 PM PDT
Verified Answers: 0
29 Sep 2011 10:33 PM PDT#1
Earlier your SRAM spec indicated that the PLL Lock time was a minimum of 1024 cycles
Now I find that the 65nm products have changed this to 20us.
what if I have an existing design that uses 1024 cycles ?
What about backward compatibility?