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How the address pin of CY7C1370D should be assigned ? | Cypress Semiconductor

How the address pin of CY7C1370D should be assigned ?

Summary: 2 Replies, Latest post by yuan.zhang_1858481 on 01 Sep 2016 12:42 AM PDT
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yuan.zhang_1858481's picture
User
2 posts

The address pins of CY7C1370D are not assigned as A2 ~ A18, they are all marked with A.

 

Please let me know how should I match those address pins to A2 ---- A18?

 

Many thanks.

Sudheesh K's picture
Cypress Employee
39 posts

The address pins (A) in Sync NoBL SRAMs can be assigned to any address bit in any order.  Two address inputs (A0) and (A1) connect to the linear burst counter and must be connected to the lower order address bits.

The data pins (DQ) also can be assigned in any order, but they must adhere to a Byte Enable grouping.  These pins are grouped by letter DQa, DQb, DQc, or DQd that corresponds to BWa, BWb, BWc, and BWd.

The parity pins (DQP), if present, are grouped with the data pins (DQ) as DQPa, DQPb, DQPc, and DQPd.  These are simply extensions of the data pin group and are also controlled by the corresponding group Byte Enable.

-Sudheesh

yuan.zhang_1858481's picture
User
2 posts

Dear Sudheesh,

Many thanks for your great answer.

Please let me ask you more questions if I have them in the future.

Best Regards.

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