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Depth Expansion of DDR2+ SRAM | Cypress Semiconductor

Depth Expansion of DDR2+ SRAM

Summary: 2 Replies, Latest post by Nosss on 19 Apr 2017 04:34 AM PDT
Verified Answers: 0
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Nosss's picture
User
8 posts

Hello. I need guidelines for depth expansion of two DDR2+ SRAMs.

Krishna GSNS's picture
Cypress Employee
197 posts

Hi Noss,

I am attaching a file showing how to connect two DDR2+  SRAMs in depth expansion. Please check the attached file.

Thanks.

 

Nosss's picture
User
8 posts

Hi Krishna,

Thanks for reference schematic. Signals CQ/CQ# from 2_DDR II+ are not connected. I can calculate the worst-case data valid window (DVW) when reading from 1_DDR II+ :

DVW = tCQHCQH - tCQHQV + tCQHQX.

How can I calculate the worst-case data valid window, when reading from 2_DDR II+, if I use echo clocks from 1_DDR II+ to capture data?

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