You are here

Depth Expansion CY7C1564XV18 | Cypress Semiconductor

Depth Expansion CY7C1564XV18

Summary: 2 Replies, Latest post by TAyresASC3D on 04 Jul 2013 01:53 PM PDT
Verified Answers: 0
Last post
Log in to post new comments.
TAyresASC3D's picture
5 posts

Looking at the application example @, I see two memories that are connected to all of the same ports, but I do not see separation of the port select lines - should there be two copies of these port select lines, one for each chip, to enable depth expansion? It looks like the setup in the application note will cause problems... have I just not had coffee yet?

prit's picture
Cypress Employee
59 posts

Hi Travis,


Nice to hear back from you!


The application example shown in the datasheet is for WIDTH EXPANSION that is why it has common select lines.

For example, you can get x72 data bus width by using two x36 devices with this setup.


But if we would like to go for DEPTH EXPANSION then of course, we need to have different selection lines (read/write) for each memory to select one of them.






TAyresASC3D's picture
5 posts

 Hi Pritesh!

Yes, that makes complete sense, thank you! 

Log in to post new comments.