CY7C1462AV33 | Cypress Semiconductor
I'm currently looking for a SRAM for my FPGA based design. The CY7C1462AV33 is a NoBL, pipelined 18x SRAM that supports up to 250MHz (i would like to use 200MHz). I have a few questions regarding that SRAM.
According to: http://www.cypress.com/?id=4&rID=30080 a single write cycle would take 2 clock cycle. Would a linear 4x writeburst take 5 clock cycle or also 2 cycle for every single write?
Since I'm using a FPGA to interface the SRAM, i want to spare as many I/O pins as possible. Is it possible to connect /CE1 and /CE3 to ground and just use CE2 as HIGH active CE?